Job Description

**Job Details:** **Job Description:** In this position you will be delivering compelling timing sign-off methodology to Intel foundry customers and enable best in class PPA on Intel technology. Working closely with EDA vendors, improve and validate flows for industry standard tools used for timing sign-off flow. Develop custom flows for validating EDA tool features. Collaborate with technology leads, VLSI physical design, and timing engineers to understand impact of variation, aging, power delivery network, etc. and deploy nuanced strategies of timing signing off. Work on various aspects of STA, constraints, timing and power optimization. **Qualifications:** You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. **Minimum Qualifications:** + MS or PhD in Electrical or Computer Engineering or related engineering field with 5+ years of experience in digital design and timing analysis. + Experience with device models and circuit yield. + Expertise in at least one of the following: extraction, device physics, STA methodology and EDA tool features. + Experience in programming with Python, Tcl, etc. **Preferred Qualifications:** + Strong communications skills + Understanding of 3DIC timing sign-off requirements. + Solid understanding of variation and statistics. + Understanding of low power design techniques like clock gating, power gating, dynamic voltage-frequency scaling (DVFS), clock domain crossing (CDC), etc. + Understanding of electro-migration, noise, jitter, etc. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Oregon, Hillsboro **Additional Locations:** US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin **Business group:** As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits:** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: Annual Salary Range for jobs which could be performed in the US: $169,820.00-$239,750.00 **S** **al** **ary** **range** **dependent on a number of factors including location and experience.** **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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